Changeset be99234 for doc/theses/thierry_delisle_PhD/thesis/fig/base.fig
- Timestamp:
- Jul 3, 2022, 9:55:28 AM (2 years ago)
- Branches:
- ADT, ast-experimental, master, pthread-emulation, qualifiedEnum
- Children:
- 84f90b6
- Parents:
- 2a859b5
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
doc/theses/thierry_delisle_PhD/thesis/fig/base.fig
r2a859b5 rbe99234 13 13 1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 6975 4200 20 20 6975 4200 6995 4200 14 14 -6 15 6 6 375 5100 6675 525016 1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 6 450 5175 20 20 6450 5175 6470 517517 1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 6 525 5175 20 20 6525 5175 6545 517518 1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 66 00 5175 20 20 6600 5175 6620 517515 6 6450 5025 6750 5175 16 1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 6525 5100 20 20 6525 5100 6545 5100 17 1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 6600 5100 20 20 6600 5100 6620 5100 18 1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 6675 5100 20 20 6675 5100 6695 5100 19 19 -6 20 20 1 3 0 1 0 7 50 -1 -1 0.000 1 0.0000 3900 2400 300 300 3900 2400 4200 2400 … … 80 80 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 81 81 2400 2475 3000 2475 82 2 3 0 1 0 7 50 -1 -1 0.000 0 0 0 0 0 783 3300 5210 3150 4950 2850 4950 2700 5210 2850 5470 3150 547084 3300 521085 2 3 0 1 0 7 50 -1 -1 0.000 0 0 0 0 0 786 4500 5210 4350 4950 4050 4950 3900 5210 4050 5470 4350 547087 4500 521088 2 3 0 1 0 7 50 -1 -1 0.000 0 0 0 0 0 789 5700 5210 5550 4950 5250 4950 5100 5210 5250 5470 5550 547090 5700 521091 82 2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 92 3600 5 700 3600 120083 3600 5400 3600 1200 93 84 2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 94 4800 5 700 4800 120085 4800 5400 4800 1200 95 86 2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 96 6000 5700 6000 1200 97 4 2 -1 50 -1 0 12 0.0000 2 135 630 2100 3075 Threads\001 98 4 2 -1 50 -1 0 12 0.0000 2 165 450 2100 2850 Ready\001 99 4 1 -1 50 -1 0 11 0.0000 2 135 180 2700 4450 TS\001 100 4 2 -1 50 -1 0 12 0.0000 2 165 720 2100 4200 Array of\001 101 4 2 -1 50 -1 0 12 0.0000 2 150 540 2100 4425 Queues\001 102 4 1 -1 50 -1 0 11 0.0000 2 135 180 2700 3550 TS\001 103 4 1 -1 50 -1 0 11 0.0000 2 135 180 2700 2650 TS\001 104 4 2 -1 50 -1 0 12 0.0000 2 135 900 2100 5175 Processors\001 87 6000 5400 6000 1200 88 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 89 2700 4800 3300 4800 3300 5400 2700 5400 2700 4800 90 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 91 3900 4800 4500 4800 4500 5400 3900 5400 3900 4800 92 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 93 5100 4800 5700 4800 5700 5400 5100 5400 5100 4800 94 4 2 -1 50 -1 0 12 0.0000 2 135 645 2100 3075 Threads\001 95 4 2 -1 50 -1 0 12 0.0000 2 180 525 2100 2850 Ready\001 96 4 1 -1 50 -1 0 11 0.0000 2 120 210 2700 4450 TS\001 97 4 2 -1 50 -1 0 12 0.0000 2 180 660 2100 4200 Array of\001 98 4 2 -1 50 -1 0 12 0.0000 2 165 600 2100 4425 Queues\001 99 4 1 -1 50 -1 0 11 0.0000 2 120 210 2700 3550 TS\001 100 4 2 -1 50 -1 0 12 0.0000 2 135 840 2100 5175 Processors\001
Note: See TracChangeset
for help on using the changeset viewer.