Changeset 7f5683e for doc/theses/thierry_delisle_PhD/code/readyQ_proto

Timestamp:

Apr 12, 2021, 5:34:33 PM (4 years ago)

Author:

Thierry Delisle <tdelisle@…>

Branches:

ADT, arm-eh, ast-experimental, enum, forall-pointer-decay, jacob/cs343-translation, master, new-ast-unique-expr, pthread-emulation, qualifiedEnum

Children:

47e000c

Parents:

a1b9bc3

Message:

Several prototype fixes for arm

Location:

doc/theses/thierry_delisle_PhD/code/readyQ_proto

Files:

• links2.hpp (modified) (2 diffs)
• processor_list.hpp (modified) (5 diffs)
• processor_list_good.cpp (modified) (1 diff)
• randbit.cpp (modified) (1 diff)
• utils.hpp (modified) (4 diffs)

doc/theses/thierry_delisle_PhD/code/readyQ_proto/links2.hpp

@@ -2 +2 @@
 
 #include <assert.h>
+
+#include "utils.hpp"
 
 //------------------------------------------------------------
@@ -36 +38 @@
 
                 // If not wait for next item to show-up, filled by push
-                while (!elem->_links.next) asm volatile("pause");
+                while (!elem->_links.next) Pause();
 
                 // we need to return if the next link was empty

doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list.hpp

@@ -39 +39 @@
                 while( __builtin_expect(ll.exchange(true),false) ) {
                         while(ll.load(std::memory_order_relaxed))
-                                asm volatile("pause");
+                                Pause();
                 }
                 /* paranoid */ assert(ll);
@@ -93 +93 @@
                          && ready.compare_exchange_weak(copy, n + 1) )
                                 break;
-                        asm volatile("pause");
+                        Pause();
                 }
 
@@ -133 +133 @@
                 // Step 1 : make sure no writer are in the middle of the critical section
                 while(lock.load(std::memory_order_relaxed))
-                        asm volatile("pause");
+                        Pause();
 
                 // Fence needed because we don't want to start trying to acquire the lock
@@ -195 +195 @@
                 //   to simply lock their own lock and enter.
                 while(lock.load(std::memory_order_relaxed))
-                        asm volatile("pause");
+                        Pause();
 
                 // Step 2 : lock per-proc lock
@@ -204 +204 @@
                 for(uint_fast32_t i = 0; i < s; i++) {
                         while(data[i].lock.load(std::memory_order_relaxed))
-                                asm volatile("pause");
+                                Pause();
                 }
 

doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list_good.cpp

@@ -21 +21 @@
                 target = (target - (target % total)) + total;
                 while(waiting < target)
-                        asm volatile("pause");
+                        Pause();
 
                 assert(waiting < (1ul << 60));

doc/theses/thierry_delisle_PhD/code/readyQ_proto/randbit.cpp

@@ -123 +123 @@
                 target = (target - (target % total)) + total;
                 while(waiting < target)
-                        asm volatile("pause");
+                        Pause();
 
                 assert(waiting < (1ul << 60));

doc/theses/thierry_delisle_PhD/code/readyQ_proto/utils.hpp

@@ -12 +12 @@
 
 #include <x86intrin.h>
-
-// Barrier from
-class barrier_t {
-public:
-        barrier_t(size_t total)
-                : waiting(0)
-                , total(total)
-        {}
-
-        void wait(unsigned) {
-                size_t target = waiting++;
-                target = (target - (target % total)) + total;
-                while(waiting < target)
-                        asm volatile("pause");
-
-                assert(waiting < (1ul << 60));
-        }
-
-private:
-        std::atomic<size_t> waiting;
-        size_t total;
-};
 
 // class Random {
@@ -102 +80 @@
 };
 
-static inline long long rdtscl(void) {
-    unsigned int lo, hi;
-    __asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
-    return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
-}
+static inline long long int rdtscl(void) {
+        #if defined( __i386 ) || defined( __x86_64 )
+                unsigned int lo, hi;
+                __asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
+                return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
+        #elif defined( __aarch64__ ) || defined( __arm__ )
+                // https://github.com/google/benchmark/blob/v1.1.0/src/cycleclock.h#L116
+                long long int virtual_timer_value;
+                asm volatile("mrs %0, cntvct_el0" : "=r"(virtual_timer_value));
+                return virtual_timer_value;
+        #else
+                #error unsupported hardware architecture
+        #endif
+}
+
+#if defined( __i386 ) || defined( __x86_64 )
+        #define Pause() __asm__ __volatile__ ( "pause" : : : )
+#elif defined( __ARM_ARCH )
+        #define Pause() __asm__ __volatile__ ( "YIELD" : : : )
+#else
+        #error unsupported architecture
+#endif
 
 static inline void affinity(int tid) {
@@ -195 +190 @@
 }
 
+// Barrier from
+class barrier_t {
+public:
+        barrier_t(size_t total)
+                : waiting(0)
+                , total(total)
+        {}
+
+        void wait(unsigned) {
+                size_t target = waiting++;
+                target = (target - (target % total)) + total;
+                while(waiting < target)
+                        Pause();
+
+                assert(waiting < (1ul << 60));
+        }
+
+private:
+        std::atomic<size_t> waiting;
+        size_t total;
+};
+
 struct spinlock_t {
         std::atomic_bool ll = { false };
@@ -201 +218 @@
                 while( __builtin_expect(ll.exchange(true),false) ) {
                         while(ll.load(std::memory_order_relaxed))
-                                asm volatile("pause");
+                                Pause();
                 }
         }