Changeset 7f5683e for doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list.hpp

Timestamp:

Apr 12, 2021, 5:34:33 PM (3 years ago)

Author:

Thierry Delisle <tdelisle@…>

Branches:

ADT, arm-eh, ast-experimental, enum, forall-pointer-decay, jacob/cs343-translation, master, new-ast-unique-expr, pthread-emulation, qualifiedEnum

Children:

47e000c

Parents:

a1b9bc3

Message:

Several prototype fixes for arm

File:

• doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list.hpp (modified) (5 diffs)

doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list.hpp

@@ -39 +39 @@
                 while( __builtin_expect(ll.exchange(true),false) ) {
                         while(ll.load(std::memory_order_relaxed))
-                                asm volatile("pause");
+                                Pause();
                 }
                 /* paranoid */ assert(ll);
@@ -93 +93 @@
                          && ready.compare_exchange_weak(copy, n + 1) )
                                 break;
-                        asm volatile("pause");
+                        Pause();
                 }
 
@@ -133 +133 @@
                 // Step 1 : make sure no writer are in the middle of the critical section
                 while(lock.load(std::memory_order_relaxed))
-                        asm volatile("pause");
+                        Pause();
 
                 // Fence needed because we don't want to start trying to acquire the lock
@@ -195 +195 @@
                 //   to simply lock their own lock and enter.
                 while(lock.load(std::memory_order_relaxed))
-                        asm volatile("pause");
+                        Pause();
 
                 // Step 2 : lock per-proc lock
@@ -204 +204 @@
                 for(uint_fast32_t i = 0; i < s; i++) {
                         while(data[i].lock.load(std::memory_order_relaxed))
-                                asm volatile("pause");
+                                Pause();
                 }