Changeset 7f5683e for doc


Ignore:
Timestamp:
Apr 12, 2021, 5:34:33 PM (3 months ago)
Author:
Thierry Delisle <tdelisle@…>
Branches:
arm-eh, jacob/cs343-translation, master
Children:
47e000c
Parents:
a1b9bc3
Message:

Several prototype fixes for arm

Location:
doc/theses/thierry_delisle_PhD/code/readyQ_proto
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • doc/theses/thierry_delisle_PhD/code/readyQ_proto/links2.hpp

    ra1b9bc3 r7f5683e  
    22
    33#include <assert.h>
     4
     5#include "utils.hpp"
    46
    57//------------------------------------------------------------
     
    3638
    3739                // If not wait for next item to show-up, filled by push
    38                 while (!elem->_links.next) asm volatile("pause");
     40                while (!elem->_links.next) Pause();
    3941
    4042                // we need to return if the next link was empty
  • doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list.hpp

    ra1b9bc3 r7f5683e  
    3939                while( __builtin_expect(ll.exchange(true),false) ) {
    4040                        while(ll.load(std::memory_order_relaxed))
    41                                 asm volatile("pause");
     41                                Pause();
    4242                }
    4343                /* paranoid */ assert(ll);
     
    9393                         && ready.compare_exchange_weak(copy, n + 1) )
    9494                                break;
    95                         asm volatile("pause");
     95                        Pause();
    9696                }
    9797
     
    133133                // Step 1 : make sure no writer are in the middle of the critical section
    134134                while(lock.load(std::memory_order_relaxed))
    135                         asm volatile("pause");
     135                        Pause();
    136136
    137137                // Fence needed because we don't want to start trying to acquire the lock
     
    195195                //   to simply lock their own lock and enter.
    196196                while(lock.load(std::memory_order_relaxed))
    197                         asm volatile("pause");
     197                        Pause();
    198198
    199199                // Step 2 : lock per-proc lock
     
    204204                for(uint_fast32_t i = 0; i < s; i++) {
    205205                        while(data[i].lock.load(std::memory_order_relaxed))
    206                                 asm volatile("pause");
     206                                Pause();
    207207                }
    208208
  • doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list_good.cpp

    ra1b9bc3 r7f5683e  
    2121                target = (target - (target % total)) + total;
    2222                while(waiting < target)
    23                         asm volatile("pause");
     23                        Pause();
    2424
    2525                assert(waiting < (1ul << 60));
  • doc/theses/thierry_delisle_PhD/code/readyQ_proto/randbit.cpp

    ra1b9bc3 r7f5683e  
    123123                target = (target - (target % total)) + total;
    124124                while(waiting < target)
    125                         asm volatile("pause");
     125                        Pause();
    126126
    127127                assert(waiting < (1ul << 60));
  • doc/theses/thierry_delisle_PhD/code/readyQ_proto/utils.hpp

    ra1b9bc3 r7f5683e  
    1212
    1313#include <x86intrin.h>
    14 
    15 // Barrier from
    16 class barrier_t {
    17 public:
    18         barrier_t(size_t total)
    19                 : waiting(0)
    20                 , total(total)
    21         {}
    22 
    23         void wait(unsigned) {
    24                 size_t target = waiting++;
    25                 target = (target - (target % total)) + total;
    26                 while(waiting < target)
    27                         asm volatile("pause");
    28 
    29                 assert(waiting < (1ul << 60));
    30         }
    31 
    32 private:
    33         std::atomic<size_t> waiting;
    34         size_t total;
    35 };
    3614
    3715// class Random {
     
    10280};
    10381
    104 static inline long long rdtscl(void) {
    105     unsigned int lo, hi;
    106     __asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
    107     return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
    108 }
     82static inline long long int rdtscl(void) {
     83        #if defined( __i386 ) || defined( __x86_64 )
     84                unsigned int lo, hi;
     85                __asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
     86                return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
     87        #elif defined( __aarch64__ ) || defined( __arm__ )
     88                // https://github.com/google/benchmark/blob/v1.1.0/src/cycleclock.h#L116
     89                long long int virtual_timer_value;
     90                asm volatile("mrs %0, cntvct_el0" : "=r"(virtual_timer_value));
     91                return virtual_timer_value;
     92        #else
     93                #error unsupported hardware architecture
     94        #endif
     95}
     96
     97#if defined( __i386 ) || defined( __x86_64 )
     98        #define Pause() __asm__ __volatile__ ( "pause" : : : )
     99#elif defined( __ARM_ARCH )
     100        #define Pause() __asm__ __volatile__ ( "YIELD" : : : )
     101#else
     102        #error unsupported architecture
     103#endif
    109104
    110105static inline void affinity(int tid) {
     
    195190}
    196191
     192// Barrier from
     193class barrier_t {
     194public:
     195        barrier_t(size_t total)
     196                : waiting(0)
     197                , total(total)
     198        {}
     199
     200        void wait(unsigned) {
     201                size_t target = waiting++;
     202                target = (target - (target % total)) + total;
     203                while(waiting < target)
     204                        Pause();
     205
     206                assert(waiting < (1ul << 60));
     207        }
     208
     209private:
     210        std::atomic<size_t> waiting;
     211        size_t total;
     212};
     213
    197214struct spinlock_t {
    198215        std::atomic_bool ll = { false };
     
    201218                while( __builtin_expect(ll.exchange(true),false) ) {
    202219                        while(ll.load(std::memory_order_relaxed))
    203                                 asm volatile("pause");
     220                                Pause();
    204221                }
    205222        }
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