Ignore:
Timestamp:
Apr 9, 2022, 2:51:24 PM (6 months ago)
Author:
Thierry Delisle <tdelisle@…>
Branches:
enum, master, pthread-emulation, qualifiedEnum
Children:
2a77817
Parents:
11a1240
Message:

Added some experiments, some graph generation and a whole lot of text

File:
1 edited

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  • doc/theses/thierry_delisle_PhD/thesis/text/eval_micro.tex

    r11a1240 r6db62fa  
    33The first step of evaluation is always to test-out small controlled cases, to ensure that the basics are working properly.
    44This sections presents five different experimental setup, evaluating some of the basic features of \CFA's scheduler.
     5
     6\section{Benchmark Environment}
     7All of these benchmarks are run on two distinct hardware environment, an AMD and an INTEL machine.
     8
     9\paragraph{AMD} The AMD machine is a server with two AMD EPYC 7662 CPUs and 256GB of DDR4 RAM.
     10The server runs Ubuntu 20.04.2 LTS on top of Linux Kernel 5.8.0-55.
     11These EPYCs have 64 cores per CPUs and 2 \glspl{hthrd} per core, for a total of 256 \glspl{hthrd}.
     12The cpus each have 4 MB, 64 MB and 512 MB of L1, L2 and L3 caches respectively.
     13Each L1 and L2 instance are only shared by \glspl{hthrd} on a given core, but each L3 instance is shared by 4 cores, therefore 8 \glspl{hthrd}.
     14
     15\paragraph{Intel} The Intel machine is a server with four Intel Xeon Platinum 8160 CPUs and 384GB of DDR4 RAM.
     16The server runs Ubuntu 20.04.2 LTS on top of Linux Kernel 5.8.0-55.
     17These Xeon Platinums have 24 cores per CPUs and 2 \glspl{hthrd} per core, for a total of 192 \glspl{hthrd}.
     18The cpus each have 3 MB, 96 MB and 132 MB of L1, L2 and L3 caches respectively.
     19Each L1 and L2 instance are only shared by \glspl{hthrd} on a given core, but each L3 instance is shared across the entire CPU, therefore 48 \glspl{hthrd}.
     20
     21This limited sharing of the last level cache on the AMD machine is markedly different than the Intel machine. Indeed, while on both architectures L2 cache misses that are served by L3 caches on a different cpu incurr a significant latency, on AMD it is also the case that cache misses served by a different L3 instance on the same cpu still incur high latency.
     22
    523
    624\section{Cycling latency}
     
    3149\end{figure}
    3250
    33 \todo{check term ``idle sleep handling''}
    3451To avoid this benchmark from being dominated by the idle sleep handling, the number of rings is kept at least as high as the number of \glspl{proc} available.
    3552Beyond this point, adding more rings serves to mitigate even more the idle sleep handling.
    36 This is to avoid the case where one of the worker \glspl{at} runs out of work because of the variation on the number of ready \glspl{at} mentionned above.
     53This is to avoid the case where one of the \glspl{proc} runs out of work because of the variation on the number of ready \glspl{at} mentionned above.
    3754
    3855The actual benchmark is more complicated to handle termination, but that simply requires using a binary semphore or a channel instead of raw \texttt{park}/\texttt{unpark} and carefully picking the order of the \texttt{P} and \texttt{V} with respect to the loop condition.
    3956
    40 \todo{code, setup, results}
    4157\begin{lstlisting}
    4258        Thread.main() {
     
    5268\end{lstlisting}
    5369
     70\begin{figure}
     71        \centering
     72        \input{result.cycle.jax.ops.pstex_t}
     73        \vspace*{-10pt}
     74        \label{fig:cycle:ns:jax}
     75\end{figure}
    5476
    5577\section{Yield}
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