Changeset 6db62fa for doc/theses/thierry_delisle_PhD/thesis/text/eval_micro.tex

Timestamp:

Apr 9, 2022, 2:51:24 PM (2 years ago)

Author:

Thierry Delisle <tdelisle@…>

Branches:

ADT, ast-experimental, enum, master, pthread-emulation, qualifiedEnum

Children:

2a77817

Parents:

11a1240

Message:

Added some experiments, some graph generation and a whole lot of text

File:

• doc/theses/thierry_delisle_PhD/thesis/text/eval_micro.tex (modified) (3 diffs)

doc/theses/thierry_delisle_PhD/thesis/text/eval_micro.tex

@@ -3 +3 @@
 The first step of evaluation is always to test-out small controlled cases, to ensure that the basics are working properly.
 This sections presents five different experimental setup, evaluating some of the basic features of \CFA's scheduler.
+
+\section{Benchmark Environment}
+All of these benchmarks are run on two distinct hardware environment, an AMD and an INTEL machine.
+
+\paragraph{AMD} The AMD machine is a server with two AMD EPYC 7662 CPUs and 256GB of DDR4 RAM.
+The server runs Ubuntu 20.04.2 LTS on top of Linux Kernel 5.8.0-55.
+These EPYCs have 64 cores per CPUs and 2 \glspl{hthrd} per core, for a total of 256 \glspl{hthrd}.
+The cpus each have 4 MB, 64 MB and 512 MB of L1, L2 and L3 caches respectively.
+Each L1 and L2 instance are only shared by \glspl{hthrd} on a given core, but each L3 instance is shared by 4 cores, therefore 8 \glspl{hthrd}.
+
+\paragraph{Intel} The Intel machine is a server with four Intel Xeon Platinum 8160 CPUs and 384GB of DDR4 RAM.
+The server runs Ubuntu 20.04.2 LTS on top of Linux Kernel 5.8.0-55.
+These Xeon Platinums have 24 cores per CPUs and 2 \glspl{hthrd} per core, for a total of 192 \glspl{hthrd}.
+The cpus each have 3 MB, 96 MB and 132 MB of L1, L2 and L3 caches respectively.
+Each L1 and L2 instance are only shared by \glspl{hthrd} on a given core, but each L3 instance is shared across the entire CPU, therefore 48 \glspl{hthrd}.
+
+This limited sharing of the last level cache on the AMD machine is markedly different than the Intel machine. Indeed, while on both architectures L2 cache misses that are served by L3 caches on a different cpu incurr a significant latency, on AMD it is also the case that cache misses served by a different L3 instance on the same cpu still incur high latency.
+
 
 \section{Cycling latency}
@@ -31 +49 @@
 \end{figure}
 
-\todo{check term ``idle sleep handling''}
 To avoid this benchmark from being dominated by the idle sleep handling, the number of rings is kept at least as high as the number of \glspl{proc} available.
 Beyond this point, adding more rings serves to mitigate even more the idle sleep handling.
-This is to avoid the case where one of the worker \glspl{at} runs out of work because of the variation on the number of ready \glspl{at} mentionned above.
+This is to avoid the case where one of the \glspl{proc} runs out of work because of the variation on the number of ready \glspl{at} mentionned above.
 
 The actual benchmark is more complicated to handle termination, but that simply requires using a binary semphore or a channel instead of raw \texttt{park}/\texttt{unpark} and carefully picking the order of the \texttt{P} and \texttt{V} with respect to the loop condition.
 
-\todo{code, setup, results}
 \begin{lstlisting}
         Thread.main() {
@@ -52 +68 @@
 \end{lstlisting}
 
+\begin{figure}
+        \centering
+        \input{result.cycle.jax.ops.pstex_t}
+        \vspace*{-10pt}
+        \label{fig:cycle:ns:jax}
+\end{figure}
 
 \section{Yield}