Changeset d6ce310

Timestamp:

Apr 7, 2026, 11:32:49 AM (6 hours ago)

Author:

Peter A. Buhr <pabuhr@…>

Branches:

master

Parents:

a0b7ef5

Message:

update experimental machine descriptions

File:

• doc/theses/mike_brooks_MMath/list.tex (modified) (1 diff)

doc/theses/mike_brooks_MMath/list.tex

@@ -821 +821 @@
 %Gigabyte E252-P31 128-core socket 3.0 GHz, WO memory model
 \item[AMD]
-Supermicro AS--1125HS--TNR EPYC 9754 128--core socket, hyper-threading $\times$ 2 sockets (512 processing units) 2.25 GHz, TSO memory model, with cache structure 32KB L1i/L1d, 1024KB L2, 16MB L3, where each L3 cache covers 16 processors.
+Supermicro AS--1125HS--TNR EPYC 9754 128--core socket, hyper-threading $\times$ 2 sockets (512 processing units) 2.25 GHz, TSO memory model, with cache structure 32KB L1i/L1d, 1024KB L2, 16MB L3, where each L3 cache covers 1 NUMA node and 8 cores (16 processors).
 \item[Intel]
-Supermicro SYS-121H-TNR Xeon Gold 6530 32--core, hyper-threading $\times$ 2 sockets (128 processing units) 2.1 GHz, TSO memory model
+Supermicro SYS-121H-TNR Xeon Gold 6530 32--core, hyper-threading $\times$ 2 sockets (128 processing units) 2.1 GHz, TSO memory model, with cache structure 32KB L1i/L1d, 20248KB L2, 160MB L3, where each L3 cache covers 2 NUMA node and 32 cores (64 processors).
 \end{description}
 The experiments are single threaded and pinned to single core to prevent any OS movement, which might cause cache or NUMA effects perturbing the experiment.