Changeset 7f8fbe3


Ignore:
Timestamp:
Nov 20, 2020, 2:16:09 PM (10 months ago)
Author:
Thierry Delisle <tdelisle@…>
Branches:
arm-eh, jacob/cs343-translation, master, new-ast-unique-expr
Children:
04994aa
Parents:
f9b2e73
Message:

Fix deadlock in cycle.go

File:
1 edited

Legend:

Unmodified
Added
Removed
  • benchmark/readyQ/cycle.go

    rf9b2e73 r7f8fbe3  
    1414        for true {
    1515                <- mine
    16                 next <- 0
     16                select {
     17                case next <- 0:
     18                default:
     19                }
    1720                count += 1
    1821                if  clock_mode && atomic.LoadInt32(&stop) == 1 { break }
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