Changeset 72b5805e

Timestamp:

Oct 19, 2022, 3:11:43 PM (21 months ago)

Author:

Thierry Delisle <tdelisle@…>

Branches:

ADT, ast-experimental, master

Children:

d1abc63c

Parents:

77de429

Message:

Fixed device/cpu to support systems without caches

Files:

• libcfa/src/device/cpu.cfa (modified) (1 diff)
• tests/device/cpu.cfa (modified) (2 diffs)

libcfa/src/device/cpu.cfa

@@ -359 +359 @@
                 int idxs = count_cache_indexes();
 
+                // Do we actually have a cache?
+                if(idxs == 0) {
+                        // if not just fake the data structure, it makes things easier.
+                        cpu_info.hthrd_count = cpus_c;
+                        cpu_info.llc_count = 0;
+                        struct cpu_map_entry_t * entries = alloc(cpu_info.hthrd_count);
+                        for(i; cpu_info.hthrd_count) {
+                                entries[i].self  = i;
+                                entries[i].start = 0;
+                                entries[i].count = cpu_info.hthrd_count;
+                                entries[i].cache = 0;
+                        }
+                        cpu_info.llc_map = entries;
+                        return;
+                }
+
                 // Count actual cache levels
                 unsigned cache_levels = 0;
                 unsigned llc = 0;
-                if (idxs != 0) {
-                        unsigned char prev = -1u;
-                        void first(unsigned idx, unsigned char level, const char * map, size_t len) {
-                                /* paranoid */ verifyf(level < prev, "Index %u of cpu 0 has cache levels out of order: %u then %u", idx, (unsigned)prev, (unsigned)level);
-                                llc = max(llc, level);
-                                prev = level;
-                                cache_levels++;
-                        }
-                        foreach_cacheidx(0, idxs, first);
-                }
+
+                unsigned char prev = -1u;
+                void first(unsigned idx, unsigned char level, const char * map, size_t len) {
+                        /* paranoid */ verifyf(level < prev, "Index %u of cpu 0 has cache levels out of order: %u then %u", idx, (unsigned)prev, (unsigned)level);
+                        llc = max(llc, level);
+                        prev = level;
+                        cache_levels++;
+                }
+                foreach_cacheidx(0, idxs, first);
 
                 // Read in raw data

tests/device/cpu.cfa

@@ -117 +117 @@
 unsigned find_idx() {
         int idxs = count_cache_indexes();
+        if( 0 == idxs ) return 0;
 
         unsigned found_level = 0;
@@ -179 +180 @@
         unsigned idx = find_idx();
         // For all procs check mapping is consistent
-        for(cpu_me; cpu_info.hthrd_count) {
+        if( idx > 0 ) for(cpu_me; cpu_info.hthrd_count) {
                 char buf_me[32];
                 size_t len_me = read_cpuidxinfo_into(cpu_me, idx, "shared_cpu_list", buf_me, 32);