1 | @ 32 bit ARM context switch |
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2 | @ This function assumes that r9 has no special meaning on the platform it's |
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3 | @ being built on. |
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4 | @ If r9 is special, uncomment the following line and it will be left alone |
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5 | |
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6 | @ #define R9_SPECIAL |
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7 | |
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8 | #define PTR_BYTE 4 |
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9 | #define SP_OFFSET ( 0 * PTR_BYTE ) |
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10 | #define FP_OFFSET ( 1 * PTR_BYTE ) |
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11 | #define PC_OFFSET ( 2 * PTR_BYTE ) |
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12 | |
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13 | .text |
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14 | .align 2 |
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15 | .global CtxSwitch |
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16 | .type CtxSwitch, %function |
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17 | |
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18 | CtxSwitch: |
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19 | @ save callee-saved registers: r4-r8, r10, r11, r13(sp) (plus r9 depending on platform specification) |
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20 | @ I've seen reference to 31 registers on 64-bit, if this is the case, more need to be saved |
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21 | @ save thread state registers: r14(lr) |
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22 | @ r12(ip) is intra-procedure-call scratch register, does not need saving between function calls |
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23 | |
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24 | #ifdef R9_SPECIAL |
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25 | stmfd r13!, {r4-r8,r10,r11,r14} |
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26 | #else |
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27 | stmfd r13!, {r4-r11,r14} |
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28 | #endif // R9_SPECIAL |
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29 | |
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30 | @ save floating point registers: s16-s31 |
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31 | vstmdb r13!, {s16-s31} |
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32 | |
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33 | @ save frame pointer and stack pointer to outgoing datastructure |
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34 | str sp, [r0, #SP_OFFSET] |
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35 | str fp, [r0, #FP_OFFSET] |
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36 | |
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37 | @ restore frame pointer and stack pointer from incoming datastructure |
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38 | ldr fp, [r1, #FP_OFFSET] |
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39 | ldr sp, [r1, #SP_OFFSET] |
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40 | |
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41 | @ restore floating point registers: s16-s31 |
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42 | vldm r13!, {s16-s31} |
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43 | @ restore r14(lr) |
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44 | @ restore 64-bit extra registers? |
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45 | @ restore callee-saved registers: r4-r8, r10, r11, r13 |
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46 | |
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47 | #ifdef R9_SPECIAL |
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48 | ldmfd r13!, {r4-r8,r10,r11,r15} |
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49 | #else |
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50 | ldmfd r13!, {r4-r11,r14} @ loading r14 back into r15 returns |
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51 | |
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52 | mov r15, r14 |
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53 | #endif // R9_SPECIAL |
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54 | |
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55 | .text |
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56 | .align 2 |
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57 | .global CtxInvokeStub |
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58 | .type CtxInvokeStub, %function |
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59 | |
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60 | CtxInvokeStub: |
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61 | ldmfd r13!, {r0-r1} |
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62 | mov r15, r1 |
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