1 | #pragma once
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2 |
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3 | #include <cassert>
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4 | #include <cstddef>
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5 | #include <atomic>
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6 | #include <chrono>
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7 | #include <fstream>
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8 | #include <iostream>
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9 |
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10 | #include <unistd.h>
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11 | #include <sys/sysinfo.h>
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12 |
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13 | #include <x86intrin.h>
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14 |
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15 | // Barrier from
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16 | class barrier_t {
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17 | public:
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18 | barrier_t(size_t total)
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19 | : waiting(0)
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20 | , total(total)
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21 | {}
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22 |
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23 | void wait(unsigned) {
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24 | size_t target = waiting++;
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25 | target = (target - (target % total)) + total;
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26 | while(waiting < target)
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27 | asm volatile("pause");
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28 |
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29 | assert(waiting < (1ul << 60));
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30 | }
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31 |
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32 | private:
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33 | std::atomic<size_t> waiting;
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34 | size_t total;
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35 | };
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36 |
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37 | class Random {
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38 | private:
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39 | unsigned int seed;
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40 | public:
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41 | Random(int seed) {
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42 | this->seed = seed;
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43 | }
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44 |
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45 | /** returns pseudorandom x satisfying 0 <= x < n. **/
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46 | unsigned int next() {
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47 | seed ^= seed << 6;
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48 | seed ^= seed >> 21;
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49 | seed ^= seed << 7;
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50 | return seed;
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51 | }
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52 | };
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53 |
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54 | static inline long long rdtscl(void) {
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55 | unsigned int lo, hi;
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56 | __asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
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57 | return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
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58 | }
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59 |
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60 | static inline void affinity(int tid) {
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61 | static int cpus = get_nprocs();
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62 |
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63 | cpu_set_t mask;
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64 | CPU_ZERO(&mask);
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65 | int cpu = cpus - tid; // Set CPU affinity to tid, starting from the end
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66 | CPU_SET(cpu, &mask);
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67 | auto result = sched_setaffinity(0, sizeof(mask), &mask);
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68 | if(result != 0) {
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69 | std::cerr << "Affinity set failed with " << result<< ", wanted " << cpu << std::endl;
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70 | }
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71 | }
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72 |
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73 | static const constexpr std::size_t cache_line_size = 64;
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74 | static inline void check_cache_line_size() {
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75 | std::cout << "Checking cache line size" << std::endl;
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76 | const std::string cache_file = "/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size";
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77 |
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78 | std::ifstream ifs (cache_file, std::ifstream::in);
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79 |
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80 | if(!ifs.good()) {
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81 | std::cerr << "Could not open file to check cache line size" << std::endl;
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82 | std::cerr << "Looking for: " << cache_file << std::endl;
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83 | std::exit(2);
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84 | }
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85 |
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86 | size_t got;
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87 | ifs >> got;
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88 |
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89 | ifs.close();
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90 |
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91 | if(cache_line_size != got) {
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92 | std::cerr << "Cache line has incorrect size : " << got << std::endl;
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93 | std::exit(1);
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94 | }
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95 |
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96 | std::cout << "Done" << std::endl;
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97 | }
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98 |
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99 | using Clock = std::chrono::high_resolution_clock;
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100 | using duration_t = std::chrono::duration<double>;
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101 | using std::chrono::nanoseconds;
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102 |
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103 | template<typename Ratio, typename T>
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104 | T duration_cast(T seconds) {
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105 | return std::chrono::duration_cast<std::chrono::duration<T, Ratio>>(std::chrono::duration<T>(seconds)).count();
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106 | }
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107 |
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108 | static inline unsigned rand_bit(unsigned rnum, size_t mask) __attribute__((artificial));
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109 | static inline unsigned rand_bit(unsigned rnum, size_t mask) {
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110 | unsigned bit = mask ? rnum % __builtin_popcountl(mask) : 0;
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111 | #if !defined(__BMI2__)
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112 | uint64_t v = mask; // Input value to find position with rank r.
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113 | unsigned int r = bit + 1;// Input: bit's desired rank [1-64].
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114 | unsigned int s; // Output: Resulting position of bit with rank r [1-64]
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115 | uint64_t a, b, c, d; // Intermediate temporaries for bit count.
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116 | unsigned int t; // Bit count temporary.
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117 |
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118 | // Do a normal parallel bit count for a 64-bit integer,
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119 | // but store all intermediate steps.
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120 | a = v - ((v >> 1) & ~0UL/3);
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121 | b = (a & ~0UL/5) + ((a >> 2) & ~0UL/5);
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122 | c = (b + (b >> 4)) & ~0UL/0x11;
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123 | d = (c + (c >> 8)) & ~0UL/0x101;
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124 |
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125 |
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126 | t = (d >> 32) + (d >> 48);
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127 | // Now do branchless select!
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128 | s = 64;
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129 | s -= ((t - r) & 256) >> 3; r -= (t & ((t - r) >> 8));
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130 | t = (d >> (s - 16)) & 0xff;
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131 | s -= ((t - r) & 256) >> 4; r -= (t & ((t - r) >> 8));
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132 | t = (c >> (s - 8)) & 0xf;
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133 | s -= ((t - r) & 256) >> 5; r -= (t & ((t - r) >> 8));
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134 | t = (b >> (s - 4)) & 0x7;
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135 | s -= ((t - r) & 256) >> 6; r -= (t & ((t - r) >> 8));
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136 | t = (a >> (s - 2)) & 0x3;
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137 | s -= ((t - r) & 256) >> 7; r -= (t & ((t - r) >> 8));
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138 | t = (v >> (s - 1)) & 0x1;
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139 | s -= ((t - r) & 256) >> 8;
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140 | return s - 1;
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141 | #else
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142 | uint64_t picked = _pdep_u64(1ul << bit, mask);
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143 | return picked ? __builtin_ctzl(picked) : 0;
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144 | #endif
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145 | }
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146 |
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147 | struct spinlock_t {
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148 | std::atomic_bool ll = { false };
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149 |
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150 | inline void lock() {
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151 | while( __builtin_expect(ll.exchange(true),false) ) {
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152 | while(ll.load(std::memory_order_relaxed))
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153 | asm volatile("pause");
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154 | }
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155 | }
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156 |
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157 | inline bool try_lock() {
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158 | return false == ll.exchange(true);
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159 | }
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160 |
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161 | inline void unlock() {
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162 | ll.store(false, std::memory_order_release);
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163 | }
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164 |
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165 | inline explicit operator bool() {
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166 | return ll.load(std::memory_order_relaxed);
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167 | }
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168 | };
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169 |
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170 | static inline bool bts(std::atomic_size_t & target, size_t bit ) {
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171 | //*
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172 | int result = 0;
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173 | asm volatile(
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174 | "LOCK btsq %[bit], %[target]\n\t"
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175 | :"=@ccc" (result)
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176 | : [target] "m" (target), [bit] "r" (bit)
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177 | );
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178 | return result != 0;
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179 | /*/
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180 | size_t mask = 1ul << bit;
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181 | size_t ret = target.fetch_or(mask, std::memory_order_relaxed);
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182 | return (ret & mask) != 0;
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183 | //*/
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184 | }
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185 |
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186 | static inline bool btr(std::atomic_size_t & target, size_t bit ) {
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187 | //*
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188 | int result = 0;
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189 | asm volatile(
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190 | "LOCK btrq %[bit], %[target]\n\t"
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191 | :"=@ccc" (result)
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192 | : [target] "m" (target), [bit] "r" (bit)
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193 | );
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194 | return result != 0;
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195 | /*/
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196 | size_t mask = 1ul << bit;
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197 | size_t ret = target.fetch_and(~mask, std::memory_order_relaxed);
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198 | return (ret & mask) != 0;
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199 | //*/
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200 | }
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