source: doc/theses/thierry_delisle_PhD/code/utils.hpp@ 1d5e4711

ADT arm-eh ast-experimental enum forall-pointer-decay jacob/cs343-translation new-ast new-ast-unique-expr pthread-emulation qualifiedEnum
Last change on this file since 1d5e4711 was 47a541d, checked in by Thierry Delisle <tdelisle@…>, 5 years ago

Add first draft of SNZI + MASK approach

  • Property mode set to 100644
File size: 4.9 KB
Line 
1#pragma once
2
3#include <cassert>
4#include <cstddef>
5#include <atomic>
6#include <chrono>
7#include <fstream>
8#include <iostream>
9
10#include <unistd.h>
11#include <sys/sysinfo.h>
12
13#include <x86intrin.h>
14
15// Barrier from
16class barrier_t {
17public:
18 barrier_t(size_t total)
19 : waiting(0)
20 , total(total)
21 {}
22
23 void wait(unsigned) {
24 size_t target = waiting++;
25 target = (target - (target % total)) + total;
26 while(waiting < target)
27 asm volatile("pause");
28
29 assert(waiting < (1ul << 60));
30 }
31
32private:
33 std::atomic<size_t> waiting;
34 size_t total;
35};
36
37class Random {
38private:
39 unsigned int seed;
40public:
41 Random(int seed) {
42 this->seed = seed;
43 }
44
45 /** returns pseudorandom x satisfying 0 <= x < n. **/
46 unsigned int next() {
47 seed ^= seed << 6;
48 seed ^= seed >> 21;
49 seed ^= seed << 7;
50 return seed;
51 }
52};
53
54static inline long long rdtscl(void) {
55 unsigned int lo, hi;
56 __asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
57 return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
58}
59
60static inline void affinity(int tid) {
61 static int cpus = get_nprocs();
62
63 cpu_set_t mask;
64 CPU_ZERO(&mask);
65 int cpu = cpus - tid; // Set CPU affinity to tid, starting from the end
66 CPU_SET(cpu, &mask);
67 auto result = sched_setaffinity(0, sizeof(mask), &mask);
68 if(result != 0) {
69 std::cerr << "Affinity set failed with " << result<< ", wanted " << cpu << std::endl;
70 }
71}
72
73static const constexpr std::size_t cache_line_size = 64;
74static inline void check_cache_line_size() {
75 std::cout << "Checking cache line size" << std::endl;
76 const std::string cache_file = "/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size";
77
78 std::ifstream ifs (cache_file, std::ifstream::in);
79
80 if(!ifs.good()) {
81 std::cerr << "Could not open file to check cache line size" << std::endl;
82 std::cerr << "Looking for: " << cache_file << std::endl;
83 std::exit(2);
84 }
85
86 size_t got;
87 ifs >> got;
88
89 ifs.close();
90
91 if(cache_line_size != got) {
92 std::cerr << "Cache line has incorrect size : " << got << std::endl;
93 std::exit(1);
94 }
95
96 std::cout << "Done" << std::endl;
97}
98
99using Clock = std::chrono::high_resolution_clock;
100using duration_t = std::chrono::duration<double>;
101using std::chrono::nanoseconds;
102
103template<typename Ratio, typename T>
104T duration_cast(T seconds) {
105 return std::chrono::duration_cast<std::chrono::duration<T, Ratio>>(std::chrono::duration<T>(seconds)).count();
106}
107
108static inline unsigned rand_bit(unsigned rnum, size_t mask) __attribute__((artificial));
109static inline unsigned rand_bit(unsigned rnum, size_t mask) {
110 unsigned bit = mask ? rnum % __builtin_popcountl(mask) : 0;
111#if !defined(__BMI2__)
112 uint64_t v = mask; // Input value to find position with rank r.
113 unsigned int r = bit + 1;// Input: bit's desired rank [1-64].
114 unsigned int s; // Output: Resulting position of bit with rank r [1-64]
115 uint64_t a, b, c, d; // Intermediate temporaries for bit count.
116 unsigned int t; // Bit count temporary.
117
118 // Do a normal parallel bit count for a 64-bit integer,
119 // but store all intermediate steps.
120 a = v - ((v >> 1) & ~0UL/3);
121 b = (a & ~0UL/5) + ((a >> 2) & ~0UL/5);
122 c = (b + (b >> 4)) & ~0UL/0x11;
123 d = (c + (c >> 8)) & ~0UL/0x101;
124
125
126 t = (d >> 32) + (d >> 48);
127 // Now do branchless select!
128 s = 64;
129 s -= ((t - r) & 256) >> 3; r -= (t & ((t - r) >> 8));
130 t = (d >> (s - 16)) & 0xff;
131 s -= ((t - r) & 256) >> 4; r -= (t & ((t - r) >> 8));
132 t = (c >> (s - 8)) & 0xf;
133 s -= ((t - r) & 256) >> 5; r -= (t & ((t - r) >> 8));
134 t = (b >> (s - 4)) & 0x7;
135 s -= ((t - r) & 256) >> 6; r -= (t & ((t - r) >> 8));
136 t = (a >> (s - 2)) & 0x3;
137 s -= ((t - r) & 256) >> 7; r -= (t & ((t - r) >> 8));
138 t = (v >> (s - 1)) & 0x1;
139 s -= ((t - r) & 256) >> 8;
140 return s - 1;
141#else
142 uint64_t picked = _pdep_u64(1ul << bit, mask);
143 return picked ? __builtin_ctzl(picked) : 0;
144#endif
145}
146
147struct spinlock_t {
148 std::atomic_bool ll = { false };
149
150 inline void lock() {
151 while( __builtin_expect(ll.exchange(true),false) ) {
152 while(ll.load(std::memory_order_relaxed))
153 asm volatile("pause");
154 }
155 }
156
157 inline bool try_lock() {
158 return false == ll.exchange(true);
159 }
160
161 inline void unlock() {
162 ll.store(false, std::memory_order_release);
163 }
164
165 inline explicit operator bool() {
166 return ll.load(std::memory_order_relaxed);
167 }
168};
169
170static inline bool bts(std::atomic_size_t & target, size_t bit ) {
171 //*
172 int result = 0;
173 asm volatile(
174 "LOCK btsq %[bit], %[target]\n\t"
175 :"=@ccc" (result)
176 : [target] "m" (target), [bit] "r" (bit)
177 );
178 return result != 0;
179 /*/
180 size_t mask = 1ul << bit;
181 size_t ret = target.fetch_or(mask, std::memory_order_relaxed);
182 return (ret & mask) != 0;
183 //*/
184}
185
186static inline bool btr(std::atomic_size_t & target, size_t bit ) {
187 //*
188 int result = 0;
189 asm volatile(
190 "LOCK btrq %[bit], %[target]\n\t"
191 :"=@ccc" (result)
192 : [target] "m" (target), [bit] "r" (bit)
193 );
194 return result != 0;
195 /*/
196 size_t mask = 1ul << bit;
197 size_t ret = target.fetch_and(~mask, std::memory_order_relaxed);
198 return (ret & mask) != 0;
199 //*/
200}
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