| [604e76d] | 1 | #FIG 3.2 Produced by xfig version 3.2.5c
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| 2 | Landscape
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| 3 | Center
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| 4 | Inches
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| 5 | Letter
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| 6 | 100.00
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| 7 | Single
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| 8 | -2
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| 9 | 1200 2
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| [d7a02ae] | 10 | 5 1 0 1 -1 -1 0 0 -1 0.000 0 1 0 0 1500.000 3600.000 1500 3300 1200 3600 1500 3900
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| 11 | 5 1 0 1 -1 -1 0 0 -1 0.000 0 1 0 0 1500.000 4500.000 1500 4200 1200 4500 1500 4800
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| 12 | 6 4200 2100 4500 2400
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| 13 | 1 3 0 1 -1 -1 0 0 -1 0.000 1 0.0000 4350 2250 105 105 4350 2250 4455 2355
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| 14 | 4 1 -1 0 0 0 10 0.0000 2 105 90 4350 2310 d\001
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| [604e76d] | 15 | -6
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| [d7a02ae] | 16 | 6 4200 1800 4500 2100
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| 17 | 1 3 0 1 -1 -1 0 0 -1 0.000 1 0.0000 4350 1950 105 105 4350 1950 4455 2055
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| 18 | 4 1 -1 0 0 0 10 0.0000 2 105 90 4350 2010 b\001
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| [604e76d] | 19 | -6
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| [d7a02ae] | 20 | 6 1420 5595 5625 5805
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| 21 | 1 3 0 1 -1 -1 0 0 20 0.000 1 0.0000 1500 5700 80 80 1500 5700 1580 5780
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| 22 | 1 3 0 1 -1 -1 0 0 -1 0.000 1 0.0000 2850 5700 105 105 2850 5700 2955 5805
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| 23 | 1 3 0 1 -1 -1 0 0 4 0.000 1 0.0000 4350 5700 105 105 4350 5700 4455 5805
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| 24 | 4 0 -1 0 0 0 12 0.0000 2 135 1035 3075 5775 blocked task\001
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| 25 | 4 0 -1 0 0 0 12 0.0000 2 135 870 1650 5775 active task\001
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| 26 | 4 0 -1 0 0 0 12 0.0000 2 135 1050 4575 5775 routine mask\001
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| [604e76d] | 27 | -6
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| [d7a02ae] | 28 | 6 3450 1950 3750 2550
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| 29 | 1 3 0 1 -1 -1 1 0 4 0.000 1 0.0000 3600 2100 105 105 3600 2100 3705 2100
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| [6d43cc57] | 30 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
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| [d7a02ae] | 31 | 3450 1950 3750 1950 3750 2550 3450 2550 3450 1950
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| 32 | 4 1 4 0 0 0 10 0.0000 2 105 120 3600 2160 Y\001
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| [604e76d] | 33 | -6
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| [d7a02ae] | 34 | 6 3450 2250 3750 2550
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| 35 | 1 3 0 1 -1 -1 1 0 4 0.000 1 0.0000 3600 2400 105 105 3600 2400 3705 2400
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| 36 | 4 1 4 0 0 0 10 0.0000 2 105 120 3600 2445 X\001
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| [604e76d] | 37 | -6
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| [d7a02ae] | 38 | 1 3 0 1 -1 -1 0 0 -1 0.000 1 0.0000 1650 3750 105 105 1650 3750 1755 3855
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| 39 | 1 3 0 1 -1 -1 0 0 -1 0.000 1 0.0000 1950 3750 105 105 1950 3750 2055 3855
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| 40 | 1 3 0 1 -1 -1 0 0 -1 0.000 1 0.0000 4950 4050 105 105 4950 4050 5055 4155
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| 41 | 1 3 0 1 -1 -1 0 0 -1 0.000 1 0.0000 5250 4050 105 105 5250 4050 5355 4155
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| 42 | 1 3 0 1 -1 -1 0 0 -1 0.000 1 0.0000 4350 2850 105 105 4350 2850 4455 2955
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| 43 | 1 3 0 1 -1 -1 0 0 -1 0.000 1 0.0000 4350 2550 105 105 4350 2550 4455 2655
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| 44 | 1 3 0 1 -1 -1 0 0 20 0.000 1 0.0000 3450 4725 80 80 3450 4725 3530 4805
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| [604e76d] | 45 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
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| [d7a02ae] | 46 | 2400 3075 3825 3075 3825 3375 2400 3375 2400 3075
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| [604e76d] | 47 | 2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 4
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| [d7a02ae] | 48 | 1500 3900 2100 3900 2100 4200 1500 4200
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| [604e76d] | 49 | 2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
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| [d7a02ae] | 50 | 1500 3600 2100 3600 2250 3825
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| [604e76d] | 51 | 2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
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| [d7a02ae] | 52 | 2100 3300 1950 3525
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| [604e76d] | 53 | 2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
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| [d7a02ae] | 54 | 1500 4500 2100 4500 2250 4725
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| [604e76d] | 55 | 2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
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| [d7a02ae] | 56 | 2100 4200 1950 4425
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| [604e76d] | 57 | 2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 4
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| [d7a02ae] | 58 | 1500 4800 2100 4800 2100 5100 3300 5100
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| [604e76d] | 59 | 2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
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| [d7a02ae] | 60 | 4800 3900 4650 4125
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| [604e76d] | 61 | 2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
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| [d7a02ae] | 62 | 3300 5100 3525 5250
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| [604e76d] | 63 | 2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 9
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| [d7a02ae] | 64 | 3600 5100 4800 5100 4800 4200 5400 4200 5400 3900 4800 3900
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| 65 | 4800 3000 4500 3000 4500 1800
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| [604e76d] | 66 | 2 2 1 1 -1 -1 0 0 -1 4.000 0 0 0 0 0 5
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| [d7a02ae] | 67 | 4200 4350 4200 3450 2700 3450 2700 4350 4200 4350
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| [6d43cc57] | 68 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
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| [604e76d] | 69 | 1 1 1.00 60.00 120.00
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| [d7a02ae] | 70 | 3600 3225 3600 2550
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| [604e76d] | 71 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
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| [d7a02ae] | 72 | 4050 3000 4500 3150
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| [6d43cc57] | 73 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
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| [d7a02ae] | 74 | 1500 3300 2100 3300 2100 3000 4050 3000 4050 1800
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| 75 | 4 1 -1 0 0 0 10 0.0000 2 75 75 4350 2895 a\001
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| 76 | 4 1 -1 0 0 0 10 0.0000 2 75 75 4350 2595 c\001
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| 77 | 4 1 -1 0 0 0 12 0.0000 2 135 315 3450 5475 exit\001
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| 78 | 4 1 -1 0 0 0 12 0.0000 2 135 135 1650 3225 A\001
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| 79 | 4 1 -1 0 0 0 12 0.0000 2 135 795 1650 5025 condition\001
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| 80 | 4 1 -1 0 0 0 12 0.0000 2 135 135 1650 5250 B\001
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| 81 | 4 0 -1 0 0 0 12 0.0000 2 135 420 4950 3825 stack\001
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| 82 | 4 0 -1 0 0 0 12 0.0000 2 180 750 4950 3375 acceptor/\001
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| 83 | 4 0 -1 0 0 0 12 0.0000 2 180 750 4950 3600 signalled\001
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| 84 | 4 1 -1 0 0 0 12 0.0000 2 135 795 1650 3000 condition\001
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| 85 | 4 0 -1 0 0 0 12 0.0000 2 135 525 4650 2550 arrival\001
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| 86 | 4 0 -1 0 0 0 12 0.0000 2 135 630 4650 2325 order of\001
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| 87 | 4 1 -1 0 0 0 12 0.0000 2 135 525 3450 3825 shared\001
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| 88 | 4 1 -1 0 0 0 12 0.0000 2 135 735 3450 4125 variables\001
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| 89 | 4 0 4 50 -1 0 11 0.0000 2 120 135 4075 2025 X\001
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| 90 | 4 0 4 50 -1 0 11 0.0000 2 120 135 4075 2325 Y\001
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| 91 | 4 0 4 50 -1 0 11 0.0000 2 120 135 4075 2625 Y\001
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| 92 | 4 0 4 50 -1 0 11 0.0000 2 120 135 4075 2925 X\001
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| 93 | 4 0 -1 0 0 3 12 0.0000 2 150 540 4950 4425 urgent\001
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| 94 | 4 1 0 50 -1 0 11 0.0000 2 165 600 3075 3300 accepted\001
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| 95 | 4 1 -1 0 0 0 12 0.0000 2 165 960 4275 1725 entry queue\001
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