Index: doc/theses/thierry_delisle_PhD/code/readyQ_proto/links2.hpp
===================================================================
--- doc/theses/thierry_delisle_PhD/code/readyQ_proto/links2.hpp	(revision a1b9bc32a15e98b204ca26969764c493704517ea)
+++ doc/theses/thierry_delisle_PhD/code/readyQ_proto/links2.hpp	(revision 7f5683e110e3e89dd201b8df0e56ae26b4a82bcd)
@@ -2,4 +2,6 @@
 
 #include <assert.h>
+
+#include "utils.hpp"
 
 //------------------------------------------------------------
@@ -36,5 +38,5 @@
 
 		// If not wait for next item to show-up, filled by push
-		while (!elem->_links.next) asm volatile("pause");
+		while (!elem->_links.next) Pause();
 
 		// we need to return if the next link was empty
Index: doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list.hpp
===================================================================
--- doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list.hpp	(revision a1b9bc32a15e98b204ca26969764c493704517ea)
+++ doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list.hpp	(revision 7f5683e110e3e89dd201b8df0e56ae26b4a82bcd)
@@ -39,5 +39,5 @@
 		while( __builtin_expect(ll.exchange(true),false) ) {
 			while(ll.load(std::memory_order_relaxed))
-				asm volatile("pause");
+				Pause();
 		}
 		/* paranoid */ assert(ll);
@@ -93,5 +93,5 @@
 			 && ready.compare_exchange_weak(copy, n + 1) )
 			 	break;
-			asm volatile("pause");
+			Pause();
 		}
 
@@ -133,5 +133,5 @@
 		// Step 1 : make sure no writer are in the middle of the critical section
 		while(lock.load(std::memory_order_relaxed))
-			asm volatile("pause");
+			Pause();
 
 		// Fence needed because we don't want to start trying to acquire the lock
@@ -195,5 +195,5 @@
 		//   to simply lock their own lock and enter.
 		while(lock.load(std::memory_order_relaxed))
-			asm volatile("pause");
+			Pause();
 
 		// Step 2 : lock per-proc lock
@@ -204,5 +204,5 @@
 		for(uint_fast32_t i = 0; i < s; i++) {
 			while(data[i].lock.load(std::memory_order_relaxed))
-				asm volatile("pause");
+				Pause();
 		}
 
Index: doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list_good.cpp
===================================================================
--- doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list_good.cpp	(revision a1b9bc32a15e98b204ca26969764c493704517ea)
+++ doc/theses/thierry_delisle_PhD/code/readyQ_proto/processor_list_good.cpp	(revision 7f5683e110e3e89dd201b8df0e56ae26b4a82bcd)
@@ -21,5 +21,5 @@
 		target = (target - (target % total)) + total;
 		while(waiting < target)
-			asm volatile("pause");
+			Pause();
 
 		assert(waiting < (1ul << 60));
Index: doc/theses/thierry_delisle_PhD/code/readyQ_proto/randbit.cpp
===================================================================
--- doc/theses/thierry_delisle_PhD/code/readyQ_proto/randbit.cpp	(revision a1b9bc32a15e98b204ca26969764c493704517ea)
+++ doc/theses/thierry_delisle_PhD/code/readyQ_proto/randbit.cpp	(revision 7f5683e110e3e89dd201b8df0e56ae26b4a82bcd)
@@ -123,5 +123,5 @@
 		target = (target - (target % total)) + total;
 		while(waiting < target)
-			asm volatile("pause");
+			Pause();
 
 		assert(waiting < (1ul << 60));
Index: doc/theses/thierry_delisle_PhD/code/readyQ_proto/utils.hpp
===================================================================
--- doc/theses/thierry_delisle_PhD/code/readyQ_proto/utils.hpp	(revision a1b9bc32a15e98b204ca26969764c493704517ea)
+++ doc/theses/thierry_delisle_PhD/code/readyQ_proto/utils.hpp	(revision 7f5683e110e3e89dd201b8df0e56ae26b4a82bcd)
@@ -12,26 +12,4 @@
 
 #include <x86intrin.h>
-
-// Barrier from
-class barrier_t {
-public:
-	barrier_t(size_t total)
-		: waiting(0)
-		, total(total)
-	{}
-
-	void wait(unsigned) {
-		size_t target = waiting++;
-		target = (target - (target % total)) + total;
-		while(waiting < target)
-			asm volatile("pause");
-
-		assert(waiting < (1ul << 60));
-    	}
-
-private:
-	std::atomic<size_t> waiting;
-	size_t total;
-};
 
 // class Random {
@@ -102,9 +80,26 @@
 };
 
-static inline long long rdtscl(void) {
-    unsigned int lo, hi;
-    __asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
-    return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
-}
+static inline long long int rdtscl(void) {
+	#if defined( __i386 ) || defined( __x86_64 )
+		unsigned int lo, hi;
+		__asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
+		return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
+	#elif defined( __aarch64__ ) || defined( __arm__ )
+		// https://github.com/google/benchmark/blob/v1.1.0/src/cycleclock.h#L116
+		long long int virtual_timer_value;
+		asm volatile("mrs %0, cntvct_el0" : "=r"(virtual_timer_value));
+		return virtual_timer_value;
+	#else
+		#error unsupported hardware architecture
+	#endif
+}
+
+#if defined( __i386 ) || defined( __x86_64 )
+	#define Pause() __asm__ __volatile__ ( "pause" : : : )
+#elif defined( __ARM_ARCH )
+	#define Pause() __asm__ __volatile__ ( "YIELD" : : : )
+#else
+	#error unsupported architecture
+#endif
 
 static inline void affinity(int tid) {
@@ -195,4 +190,26 @@
 }
 
+// Barrier from
+class barrier_t {
+public:
+	barrier_t(size_t total)
+		: waiting(0)
+		, total(total)
+	{}
+
+	void wait(unsigned) {
+		size_t target = waiting++;
+		target = (target - (target % total)) + total;
+		while(waiting < target)
+			Pause();
+
+		assert(waiting < (1ul << 60));
+    	}
+
+private:
+	std::atomic<size_t> waiting;
+	size_t total;
+};
+
 struct spinlock_t {
 	std::atomic_bool ll = { false };
@@ -201,5 +218,5 @@
 		while( __builtin_expect(ll.exchange(true),false) ) {
 			while(ll.load(std::memory_order_relaxed))
-				asm volatile("pause");
+				Pause();
 		}
 	}