Index: doc/theses/thierry_delisle_PhD/comp_II/comp_II.tex
===================================================================
--- doc/theses/thierry_delisle_PhD/comp_II/comp_II.tex	(revision 0254454f7ce41ce55f28a2408a01e5898ba7afbc)
+++ doc/theses/thierry_delisle_PhD/comp_II/comp_II.tex	(revision 7cfef0d3591be55e19b3b055bf50d7d4c19e3699)
@@ -44,5 +44,4 @@
 \begin{document}
 \maketitle
-\thispagestyle{empty}
 \cleardoublepage
 
@@ -328,5 +327,5 @@
 
 How much scalability is actually needed is highly debatable.
-\emph{libfibre}\cite{libfibre} has compared favorably to other schedulers in webserver tests\cite{Karsten20} and uses a single atomic counter in its scheduling algorithm similarly to the proposed bitmask.
+\emph{libfibre}\cite{libfibre} has compared favorably to other schedulers in webserver tests\cite{karstenuser} and uses a single atomic counter in its scheduling algorithm similarly to the proposed bitmask.
 As such, the single atomic instruction on a shared cacheline may be sufficiently performant.
 
@@ -422,5 +421,5 @@
 Processors that are unnecessarily unblocked lead to unnecessary contention, CPU usage, and power consumption, while too many sleeping processors can lead to sub-optimal throughput.
 Furthermore, transitions from sleeping to awake and vice-versa also add unnecessary latency.
-There is already a wealth of research on the subject\cite{schillings1996engineering, wiki:thunderherd} and I may use an existing approach for the idle-sleep heuristic in this project, \eg\cite{Karsten20}.
+There is already a wealth of research on the subject\cite{schillings1996engineering, wiki:thunderherd} and I may use an existing approach for the idle-sleep heuristic in this project, \eg\cite{karstenuser}.
 
 \subsection{Asynchronous I/O}
Index: libcfa/src/concurrency/CtxSwitch-arm.S
===================================================================
--- libcfa/src/concurrency/CtxSwitch-arm.S	(revision 7cfef0d3591be55e19b3b055bf50d7d4c19e3699)
+++ libcfa/src/concurrency/CtxSwitch-arm.S	(revision 7cfef0d3591be55e19b3b055bf50d7d4c19e3699)
@@ -0,0 +1,104 @@
+// 
+// Cforall Version 1.0.0 Copyright (C) 2016 University of Waterloo
+// 
+// CtxSwitch-arm.S -- 
+// 
+// Author           : Peter A. Buhr
+// Created On       : Sun Aug 16 07:50:13 2020
+// Last Modified By : Peter A. Buhr
+// Last Modified On : Thu Aug 20 18:43:51 2020
+// Update Count     : 24
+// 
+
+// The context switch routine requires the initial the stack of a thread to
+// look like the thread has saved its context in the normal manner.
+
+// Offsets must synchronized with the __stack_context_t in invoke.h.
+
+#define PTR_BYTE	8
+#define SP_OFFSET	( 0 * PTR_BYTE )
+#define FP_OFFSET	( 1 * PTR_BYTE )
+
+// Context switch between coroutines/tasks.
+//   void __cfactx_switch( struct __stack_context_t * from, struct __stack_context_t * to ) ;
+// Arguments "from" in register x0, "to" in register x1.
+
+#define SAVE		20 * 8
+
+	.file "CtxSwitch-arm.S"
+	.text
+	.align 2
+	.global __cfactx_switch
+	.type __cfactx_switch, @function
+__cfactx_switch:
+
+	sub  sp, sp, #SAVE					// push stack
+
+	// Save volatile GP registers x19-x30 on the stack.
+
+	stp  x19, x20, [sp, #0x00]
+	stp  x21, x22, [sp, #0x10]
+	stp  x23, x24, [sp, #0x20]
+	stp  x25, x26, [sp, #0x30]
+	stp  x27, x28, [sp, #0x40]
+	stp  x29, x30, [sp, #0x50]			// x29 => fp
+
+	// Save volatile SIMD/FPU registers d8-d15 on the stack.
+
+	stp  d8,  d9,  [sp, #0x60]
+	stp  d10, d11, [sp, #0x70]
+	stp  d12, d13, [sp, #0x80]
+	stp  d14, d15, [sp, #0x90]
+
+	// Save old context in the "from" area.
+
+	mov  x4, sp							// cannot store sp directly
+	str  x4, [x0, #SP_OFFSET]
+	str  fp, [x0, #FP_OFFSET]
+
+	// Load new context from the "to" area.
+
+	ldr  fp, [x1, #FP_OFFSET]
+	ldr  x4, [x1, #SP_OFFSET]
+	mov  sp, x4							// cannot store sp directly
+
+	// Load volatile GP registers x19-x30 from the stack.
+
+	ldp  x19, x20, [sp, #0x00]
+	ldp  x21, x22, [sp, #0x10]
+	ldp  x23, x24, [sp, #0x20]
+	ldp  x25, x26, [sp, #0x30]
+	ldp  x27, x28, [sp, #0x40]
+	ldp  x29, x30, [sp, #0x50]
+	
+	// Load volatile SIMD/FPU registers d8-d15 from the stack.
+
+	ldp  d8,  d9,  [sp, #0x60]
+	ldp  d10, d11, [sp, #0x70]
+	ldp  d12, d13, [sp, #0x80]
+	ldp  d14, d15, [sp, #0x90]
+
+	add  sp, sp, #SAVE					// pop stack
+	ret									// return to new thread (mov pc, x30)
+
+	.size __cfactx_switch, .-__cfactx_switch
+	.section .note.GNU-stack,"",%progbits // mark no executable stack needed
+
+// Stub to create new stacks which can be context switched to
+//   void __cfactx_invoke_stub( void );
+
+	.text
+	.align 2
+	.global __cfactx_invoke_stub
+	.type __cfactx_invoke_stub, @function
+__cfactx_invoke_stub:
+	mov x0, x19							// load main as parameter 0
+	mov x1, x20							// load this as parameter 1
+	mov x30, x21						// load coroutine invoke routine
+	ret									//   and jmp to it (mov pc, x30)
+	.size __cfactx_invoke_stub, .-__cfactx_invoke_stub
+
+// Local Variables: //
+// mode: c //
+// tab-width: 4 //
+// End: //
Index: bcfa/src/concurrency/CtxSwitch-arm64.S
===================================================================
--- libcfa/src/concurrency/CtxSwitch-arm64.S	(revision 0254454f7ce41ce55f28a2408a01e5898ba7afbc)
+++ 	(revision )
@@ -1,104 +1,0 @@
-// 
-// Cforall Version 1.0.0 Copyright (C) 2016 University of Waterloo
-// 
-// CtxSwitch-arm.S -- 
-// 
-// Author           : Peter A. Buhr
-// Created On       : Sun Aug 16 07:50:13 2020
-// Last Modified By : Peter A. Buhr
-// Last Modified On : Thu Aug 20 18:43:51 2020
-// Update Count     : 24
-// 
-
-// The context switch routine requires the initial the stack of a thread to
-// look like the thread has saved its context in the normal manner.
-
-// Offsets must synchronized with the __stack_context_t in invoke.h.
-
-#define PTR_BYTE	8
-#define SP_OFFSET	( 0 * PTR_BYTE )
-#define FP_OFFSET	( 1 * PTR_BYTE )
-
-// Context switch between coroutines/tasks.
-//   void __cfactx_switch( struct __stack_context_t * from, struct __stack_context_t * to ) ;
-// Arguments "from" in register x0, "to" in register x1.
-
-#define SAVE		20 * 8
-
-	.file "CtxSwitch-arm.S"
-	.text
-	.align 2
-	.global __cfactx_switch
-	.type __cfactx_switch, @function
-__cfactx_switch:
-
-	sub  sp, sp, #SAVE					// push stack
-
-	// Save volatile GP registers x19-x30 on the stack.
-
-	stp  x19, x20, [sp, #0x00]
-	stp  x21, x22, [sp, #0x10]
-	stp  x23, x24, [sp, #0x20]
-	stp  x25, x26, [sp, #0x30]
-	stp  x27, x28, [sp, #0x40]
-	stp  x29, x30, [sp, #0x50]			// x29 => fp
-
-	// Save volatile SIMD/FPU registers d8-d15 on the stack.
-
-	stp  d8,  d9,  [sp, #0x60]
-	stp  d10, d11, [sp, #0x70]
-	stp  d12, d13, [sp, #0x80]
-	stp  d14, d15, [sp, #0x90]
-
-	// Save old context in the "from" area.
-
-	mov  x4, sp							// cannot store sp directly
-	str  x4, [x0, #SP_OFFSET]
-	str  fp, [x0, #FP_OFFSET]
-
-	// Load new context from the "to" area.
-
-	ldr  fp, [x1, #FP_OFFSET]
-	ldr  x4, [x1, #SP_OFFSET]
-	mov  sp, x4							// cannot store sp directly
-
-	// Load volatile GP registers x19-x30 from the stack.
-
-	ldp  x19, x20, [sp, #0x00]
-	ldp  x21, x22, [sp, #0x10]
-	ldp  x23, x24, [sp, #0x20]
-	ldp  x25, x26, [sp, #0x30]
-	ldp  x27, x28, [sp, #0x40]
-	ldp  x29, x30, [sp, #0x50]
-	
-	// Load volatile SIMD/FPU registers d8-d15 from the stack.
-
-	ldp  d8,  d9,  [sp, #0x60]
-	ldp  d10, d11, [sp, #0x70]
-	ldp  d12, d13, [sp, #0x80]
-	ldp  d14, d15, [sp, #0x90]
-
-	add  sp, sp, #SAVE					// pop stack
-	ret									// return to new thread (mov pc, x30)
-
-	.size __cfactx_switch, .-__cfactx_switch
-	.section .note.GNU-stack,"",%progbits // mark no executable stack needed
-
-// Stub to create new stacks which can be context switched to
-//   void __cfactx_invoke_stub( void );
-
-	.text
-	.align 2
-	.global __cfactx_invoke_stub
-	.type __cfactx_invoke_stub, @function
-__cfactx_invoke_stub:
-	mov x0, x19							// load main as parameter 0
-	mov x1, x20							// load this as parameter 1
-	mov x30, x21						// load coroutine invoke routine
-	ret									//   and jmp to it (mov pc, x30)
-	.size __cfactx_invoke_stub, .-__cfactx_invoke_stub
-
-// Local Variables: //
-// mode: c //
-// tab-width: 4 //
-// End: //
Index: tests/pybin/settings.py
===================================================================
--- tests/pybin/settings.py	(revision 0254454f7ce41ce55f28a2408a01e5898ba7afbc)
+++ tests/pybin/settings.py	(revision 7cfef0d3591be55e19b3b055bf50d7d4c19e3699)
@@ -27,22 +27,16 @@
 		'x86_64'      : 'x64',
 		'x86'         : 'x86',
-		'aarch64'     : 'arm64',
-		'arm64'       : 'arm64',
-		'ARM64'       : 'arm64',
+		'aarch64'     : 'arm',
 		'i386'        : 'x86',
 		'i486'        : 'x86',
 		'i686'        : 'x86',
 		'Intel 80386' : 'x86',
-		'arm'         : 'arm32',
-		'ARM'         : 'arm32',
-		'arm32'       : 'arm32',
-		'ARM32'       : 'arm32',
+		'arm'         : 'arm',
+		'ARM'         : 'arm',
 	}
 
 	CrossCompileFlags = {
-		'x64'  : 'ARCH_FLAGS=-m64',
-		'x86'  : 'ARCH_FLAGS=-m32',
-		'arm64': 'ARCH_FLAGS=',
-		'arm32': 'ARCH_FLAGS=',
+		'x64' : 'ARCH_FLAGS=-m64',
+		'x86' : 'ARCH_FLAGS=-m32',
 	}
 
Index: tools/build/cfa.m4
===================================================================
--- tools/build/cfa.m4	(revision 0254454f7ce41ce55f28a2408a01e5898ba7afbc)
+++ tools/build/cfa.m4	(revision 7cfef0d3591be55e19b3b055bf50d7d4c19e3699)
@@ -66,7 +66,5 @@
 		"x86-64"     ) cannon_arch_name="x64";;
 		"x86_64"     ) cannon_arch_name="x64";;
-		"aarch64"    ) cannon_arch_name="arm64";;
-		"arm4"       ) cannon_arch_name="arm64";;
-		"ARM64"      ) cannon_arch_name="arm64";;
+		"aarch64"    ) cannon_arch_name="arm";;
 		"x86"        ) cannon_arch_name="x86";;
 		"i386"       ) cannon_arch_name="x86";;
@@ -74,9 +72,7 @@
 		"i686"       ) cannon_arch_name="x86";;
 		"Intel 80386") cannon_arch_name="x86";;
-		"arm"        ) cannon_arch_name="arm32";;
-		"ARM"        ) cannon_arch_name="arm32";;
-		"arm32"      ) cannon_arch_name="arm32";;
-		"ARM32"      ) cannon_arch_name="arm32";;
-		"armv7l"     ) cannon_arch_name="arm32";;
+		"arm"        ) cannon_arch_name="arm";;
+		"ARM"        ) cannon_arch_name="arm";;
+		"armv7l"     ) cannon_arch_name="arm";;
 		*)
 		>&2 echo "Unknown architecture " $arch_name;
